Current and future three-dimensional LSI integration technology by "chip on chip", "chip on wafer" and "wafer on wafer"

Manabu Bonkohara; Makoto Motoyoshi; Kazutoshi Kamibayashi; Mitsumasa Koyanagi

Current and future three-dimensional LSI integration technology by "chip on chip", "chip on wafer" and "wafer on wafer"

Manabu Bonkohara, Makoto Motoyoshi, Kazutoshi Kamibayashi, Mitsumasa Koyanagi

未来科学技術共同研究センター

研究成果: Conference contribution

11 被引用数 (Scopus)

抄録

Recently the development of three dimensional LSI (3D-LSI) has been accelerated and its stage has changed from the research level or limited production level to the investigation level with a view to mass production. This paper describes the current and the future 3D-LSI technologies which we have considered and imagined. The current technology is represented by our Chip Size Package (CSP) for sensor device, for instance. In the future technology, there are five key technologies described. We consider the pros and cons of the current 3D LSI stacked approach, such as CoC (Chip on Chip), CoW (Chip on Wafer) and WoW (Wafer on Wafer). We confirmed that CoW combined with Super-Smart-Stack (SSS™) technology will shorten the process time per chip at the same level as WoW approach and is effective to minimize process cost.

本文言語	English
ホスト出版物のタイトル	Enabling Technologies for 3-D Integration
ページ	35-45
ページ数	11
出版ステータス	Published - 2007 6月 29
イベント	2006 MRS Fall Meeting - Boston, MA, United States 継続期間: 2006 11月 27 → 2006 11月 29

出版物シリーズ

名前	Materials Research Society Symposium Proceedings
巻	970
ISSN（印刷版）	0272-9172

Other

Other	2006 MRS Fall Meeting
国/地域	United States
City	Boston, MA
Period	06/11/27 → 06/11/29

ASJC Scopus subject areas

材料科学（全般）
凝縮系物理学
材料力学
機械工学

他のファイルとリンク

引用スタイル

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abstract = "Recently the development of three dimensional LSI (3D-LSI) has been accelerated and its stage has changed from the research level or limited production level to the investigation level with a view to mass production. This paper describes the current and the future 3D-LSI technologies which we have considered and imagined. The current technology is represented by our Chip Size Package (CSP) for sensor device, for instance. In the future technology, there are five key technologies described. We consider the pros and cons of the current 3D LSI stacked approach, such as CoC (Chip on Chip), CoW (Chip on Wafer) and WoW (Wafer on Wafer). We confirmed that CoW combined with Super-Smart-Stack (SSS{\texttrademark}) technology will shorten the process time per chip at the same level as WoW approach and is effective to minimize process cost.",

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AU - Motoyoshi, Makoto

AU - Kamibayashi, Kazutoshi

AU - Koyanagi, Mitsumasa

PY - 2007/6/29

Y1 - 2007/6/29

N2 - Recently the development of three dimensional LSI (3D-LSI) has been accelerated and its stage has changed from the research level or limited production level to the investigation level with a view to mass production. This paper describes the current and the future 3D-LSI technologies which we have considered and imagined. The current technology is represented by our Chip Size Package (CSP) for sensor device, for instance. In the future technology, there are five key technologies described. We consider the pros and cons of the current 3D LSI stacked approach, such as CoC (Chip on Chip), CoW (Chip on Wafer) and WoW (Wafer on Wafer). We confirmed that CoW combined with Super-Smart-Stack (SSS™) technology will shorten the process time per chip at the same level as WoW approach and is effective to minimize process cost.

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BT - Enabling Technologies for 3-D Integration

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Current and future three-dimensional LSI integration technology by "chip on chip", "chip on wafer" and "wafer on wafer"

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出版物シリーズ

Other

ASJC Scopus subject areas

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