This paper presents a unified representation of fast addition algorithms based on Counter Tree Diagrams (CTDs). By using CTDs, we can describe and analyze various adder architectures in a systematic way without using specific knowledge about underlying arithmetic algorithms. Examples of adder architectures that can be handled by CTDs include Redundant-Binary (RB) adders, Signed-Digit (SD) adders, Positive-Digit (PD) or carry-save adders, parallel counters (e.g., 3-2 counters and 4-2 counters) and networks of such basic adders/counters. This paper also discusses the CTD-based design and analysis of carry-propagation-free adders using redundant number representation.
|ジャーナル||Proceedings of The International Symposium on Multiple-Valued Logic|
|出版ステータス||Published - 2003 7 21|
|イベント||Thirty-third International Symposium on Multiple-Valued Logic - Tokyo, Japan|
継続期間: 2003 5 16 → 2003 5 19
ASJC Scopus subject areas
- コンピュータ サイエンス（全般）
- 数学 (全般)