Counter tree diagrams for design and analysis of fast addition algorithms

Jun Sakiyama, Takafumi Aoki, Tatsuo Higuchi

研究成果: Conference article査読

7 被引用数 (Scopus)

抄録

This paper presents a unified representation of fast addition algorithms based on Counter Tree Diagrams (CTDs). By using CTDs, we can describe and analyze various adder architectures in a systematic way without using specific knowledge about underlying arithmetic algorithms. Examples of adder architectures that can be handled by CTDs include Redundant-Binary (RB) adders, Signed-Digit (SD) adders, Positive-Digit (PD) or carry-save adders, parallel counters (e.g., 3-2 counters and 4-2 counters) and networks of such basic adders/counters. This paper also discusses the CTD-based design and analysis of carry-propagation-free adders using redundant number representation.

本文言語English
ページ(範囲)91-98
ページ数8
ジャーナルProceedings of The International Symposium on Multiple-Valued Logic
出版ステータスPublished - 2003 7 21
イベントThirty-third International Symposium on Multiple-Valued Logic - Tokyo, Japan
継続期間: 2003 5 162003 5 19

ASJC Scopus subject areas

  • コンピュータ サイエンス(全般)
  • 数学 (全般)

フィンガープリント

「Counter tree diagrams for design and analysis of fast addition algorithms」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル