This paper describes a high-performance VLSI processor for the collision detection of intelligent vehicles. In the collision detection, high-computational power is essential in not only coordinate transformation but also matching operation between vehicle and obstacle pixels. In the processor, a content-addressable memory is introduced to store vehicle pixel information, so that the matching operation is drastically accelerated. Since vehicle pixel information is predetermined and not changed, the high-performance CAM based on a ROM cell is proposed. A parallel and pipelined architecture for the high-speed coordinate transformation is also proposed based on two-dimensional vector rotations and matrix multiplications.
|出版ステータス||Published - 1996 12月 1|
|イベント||Proceedings of the 1996 IEEE 22nd International Conference on Industrial Electronics, Control, and Instrumentation, IECON. Part 2 (of 3) - Taipei, Taiwan|
継続期間: 1996 8月 5 → 1996 8月 10
|Other||Proceedings of the 1996 IEEE 22nd International Conference on Industrial Electronics, Control, and Instrumentation, IECON. Part 2 (of 3)|
|Period||96/8/5 → 96/8/10|
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