Clock-controlled neuron-mos logic gates

Koji Kotani

研究成果: Article査読

40 被引用数 (Scopus)

抄録

A new clock-controlled circuit scheme has been introduced in the basic architecture of neuron-MOS (neuMOS or f MOS) logic gates. In this scheme, the charge on a neuMOS floating gate is periodically refreshed by a clock-controlled switch. A special refreshing scheme in which fluctuations in device parameters are automatically canceled has been employed. As a result, the number of multiple logic levels that can be handled in a neuMOS floating gate has been increased. In addition, the data subtraction operation directly conducted on the floating gate has become possible. All of these circuit techniques have enhanced the functionality of a neuMOS logic gate a great deal. In order to achieve a low power operation, latched-sense-amplifler circuitries are also introduced for logic decision. Test circuits were fabricated in a double-polysilicon CMOS process, and the basic circuit operations are demonstrated.

本文言語English
ページ(範囲)518-522
ページ数5
ジャーナルIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
45
4
DOI
出版ステータスPublished - 1998
外部発表はい

ASJC Scopus subject areas

  • 信号処理
  • 電子工学および電気工学

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