A new clock-controlled circuit scheme has been introduced in the basic architecture of neuron-MOS (neuMOS or f MOS) logic gates. In this scheme, the charge on a neuMOS floating gate is periodically refreshed by a clock-controlled switch. A special refreshing scheme in which fluctuations in device parameters are automatically canceled has been employed. As a result, the number of multiple logic levels that can be handled in a neuMOS floating gate has been increased. In addition, the data subtraction operation directly conducted on the floating gate has become possible. All of these circuit techniques have enhanced the functionality of a neuMOS logic gate a great deal. In order to achieve a low power operation, latched-sense-amplifler circuitries are also introduced for logic decision. Test circuits were fabricated in a double-polysilicon CMOS process, and the basic circuit operations are demonstrated.
|ジャーナル||IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing|
|出版ステータス||Published - 1998|
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