Chip-level TSV integration for rapid prototyping of 3D system LSIs

Kazuyuki Hozawa, Futoshi Furuta, Yuko Hanaoka, Mayu Aoki, Kenichi Takeda, Katsuyuki Sakuma, Kanuku Ri, Takafumi Fukushima, Mitsumasa Koyanagi

研究成果: Conference contribution

抄録

For rapid prototyping of system LSIs based on three-dimension (3D) integration using through-silicon-vias (TSVs), a TSV fabrication technology for a diced chip with copper/low-k interconnections (called "chip-level TSV integration") was developed. The two key processes of this technology are uniform substrate thinning in chip form and via-last TSV formation for nanometer-sized copper/low-k interconnection. Chip-level TSV integration will provide rapid prototyping of 3D system LSIs based on various chips with TSVs.

本文言語English
ホスト出版物のタイトル2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
DOI
出版ステータスPublished - 2011 12 1
イベント2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 - Osaka, Japan
継続期間: 2012 1 312012 2 2

出版物シリーズ

名前2011 IEEE International 3D Systems Integration Conference, 3DIC 2011

Other

Other2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
国/地域Japan
CityOsaka
Period12/1/3112/2/2

ASJC Scopus subject areas

  • 制御およびシステム工学

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