Challenges in 3D integration

Mitsumasa Koyanagi, Kang Wook Lee, Takafumi Fukushima, Tetsu Tanaka

研究成果: Conference contribution

3 被引用数 (Scopus)

抄録

Three-dimensional (3D) LSIs using TSVs are indispensable to achieve high performance and low power LSIs with smaller form factor. A wafer-to-wafer (WtW) technology is suitable for stacking chips with high production yield such as DRAM since the overall yield after stacking rapidly decreases as the number of stacking layers increases. The chip-to-wafer (CtW) is suitable for stacking known good dies (KGDs). In addition, chips with different size which are fabricated using different process technologies can be stacked in the CtW technology. The inherent problem in the CtW technology, however, is low production throughput. To solve these problems, we have proposed a new 3D heterogeneous integration technology called a super-chip technology using self-assembly and electrostatic (SAE) bonding method.

本文言語English
ホスト出版物のタイトルSilicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 3
ページ237-244
ページ数8
3
DOI
出版ステータスPublished - 2013
イベントInternational Symposium on Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 3 - 223rd ECS Meeting - Toronto, ON, Canada
継続期間: 2013 5月 122013 5月 17

出版物シリーズ

名前ECS Transactions
番号3
53
ISSN(印刷版)1938-5862
ISSN(電子版)1938-6737

Other

OtherInternational Symposium on Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 3 - 223rd ECS Meeting
国/地域Canada
CityToronto, ON
Period13/5/1213/5/17

ASJC Scopus subject areas

  • 工学(全般)

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