This paper proposes a highly parallel algorithm of separable denominator two‐dimensional (2‐D) state‐space digital filters, called a block parallel algorithm. to derive the block parallel algorithm, the processing image is divided into several blocks and all dependency constraints in a divided block are eliminated. In the block parallel algorithm, the number of multiply‐and‐accumulate operations required to process one image is proportional to 1/L for the block length L. We also study the architecture of the block processor which implements our proposed algorithm. As a result, one 250‐K gates VLSI chip to implement one block processor with the block length L = 8 must be designed. the multiprocessor system comprising 66 proposed VLSI chips can propose 2048 × 2048 pixels image at the rate of 60 frames/s.
|ジャーナル||Electronics and Communications in Japan (Part III: Fundamental Electronic Science)|
|出版物ステータス||Published - 1995 2|
ASJC Scopus subject areas
- Electrical and Electronic Engineering