Beyond-binary circuits for signal processing

T. Hanyu, M. Kameyama, T. Higuchi

研究成果: Conference contribution

11 被引用数 (Scopus)

抄録

Several basic arithmetic and logic modules based on MVL (multiple-valued logic), including a multiplier and a pattern-matching accelerator, are presented. A micrograph of a 32-b∗32-b SD (signed-digit) multiplier using multiple-valued bidirectional current-mode circuits is shown. Carry propagation during addition and subtraction is limited to one position to the left, providing totally parallel operation. Linear summation is simply by wiring. A mod-7 three-operand multiplier-Adder based on residue arithmetic is also shown. Each residue digit is represented by a multiple-valued coding suitable for highly parallel computation, making it possible to achieve high-speed arithmetic operations. A quaternary nMOS logic-Array chip for high-speed parallel pattern matching in a knowledge-information processing system is also shown. In addition, as an example of multiple-valued VLSI processors, a parallel-structure-based multiple-valued VLSI processor for high-performance digital control is shown.

本文言語English
ホスト出版物のタイトル1993 IEEE International Solid-State Circuits Conference, ISSCC 1993 - Digest of Technical Papers
出版社Institute of Electrical and Electronics Engineers Inc.
ページ134-135
ページ数2
ISBN(電子版)0780309871
DOI
出版ステータスPublished - 1993 1月 1
イベント40th IEEE International Solid-State Circuits Conference, ISSCC 1993 - San Francisco, United States
継続期間: 1993 2月 241993 2月 26

出版物シリーズ

名前Digest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN(印刷版)0193-6530

Conference

Conference40th IEEE International Solid-State Circuits Conference, ISSCC 1993
国/地域United States
CitySan Francisco
Period93/2/2493/2/26

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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