Benchmarks for FPGA-Targeted High-Level-Synthesis

研究成果: Conference contribution

抄録

Recently, high-level synthesis (HLS) tools such as 'Intel FPGA SDK for OpenCL" and 'Xilinx SDAccel' have been introduced to design FPGA accelerators. Those HLS tools use 'C language' based environment to significantly reduce the design time. However, it is also important to know how much performance we can achieve using HLS tools. FPGA is a highly reconfigurable hardware and the performances are extremely different depending on the architecture. Performances also depend on the FPGA board, HLS software and firmware such as BSP (board support package). Therefore, benchmarking FPGAs is an extremely challenging task. This paper proposes a method to design benchmarks for FPGA-targeted HLS. The benchmarks are highly scalable and can be used for different FPGAs and compilers to obtain most of the potential performance. Evaluating four different FPGAs, we found that the single-precision floating-point computation performance varies from 17 GFLOPS to 3,955 GFLOPS depending on the operation and the FPGA. We have obtained 64% and 43% of the peak performance of single-precision computation for Arria 10 and Stratix 10 FPGAs respectively. The fixed-point computation performance heavily depends on the bit size and varies from 8 GOPS to 12,800 GOPS.

本文言語English
ホスト出版物のタイトルProceedings - 2019 7th International Symposium on Computing and Networking, CANDAR 2019
出版社Institute of Electrical and Electronics Engineers Inc.
ページ232-238
ページ数7
ISBN(電子版)9781728147253
DOI
出版ステータスPublished - 2019 11
イベント7th International Symposium on Computing and Networking, CANDAR 2019 - Nagasaki, Japan
継続期間: 2019 11 262019 11 29

出版物シリーズ

名前Proceedings - 2019 7th International Symposium on Computing and Networking, CANDAR 2019

Conference

Conference7th International Symposium on Computing and Networking, CANDAR 2019
国/地域Japan
CityNagasaki
Period19/11/2619/11/29

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用
  • コンピュータ ネットワークおよび通信
  • ハードウェアとアーキテクチャ
  • 信号処理

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