Automatic generation of formally-proven tamper-resistant Galois-field multipliers based on generalized masking scheme

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

In this study, we propose a formal design system for tamper-resistant cryptographic hardwares based on Generalized Masking Scheme (GMS). The masking scheme, which is a state-of-the-art masking-based countermeasure against higher-order differential power analyses (DPAs), can securely construct any kind of Galois-field (GF) arithmetic circuits at the register transfer level (RTL) description, while most other ones require specific physical design. In this study, we first present a formal design methodology of GMS-based GF arithmetic circuits based on a hierarchical dataflow graph, called GF arithmetic circuit graph (GF-ACG), and present a formal verification method for both functionality and security property based on Gröbner basis. In addition, we propose an automatic generation system for GMS-based GF multipliers, which can synthesize a fifth-order 256-bit multiplier (whose input bit-length is 256 × 77) within 15 min.

本文言語English
ホスト出版物のタイトルProceedings of the 2017 Design, Automation and Test in Europe, DATE 2017
出版社Institute of Electrical and Electronics Engineers Inc.
ページ978-983
ページ数6
ISBN(電子版)9783981537093
DOI
出版ステータスPublished - 2017 5 11
イベント20th Design, Automation and Test in Europe, DATE 2017 - Swisstech, Lausanne, Switzerland
継続期間: 2017 3 272017 3 31

出版物シリーズ

名前Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017

Other

Other20th Design, Automation and Test in Europe, DATE 2017
国/地域Switzerland
CitySwisstech, Lausanne
Period17/3/2717/3/31

ASJC Scopus subject areas

  • コンピュータ ネットワークおよび通信
  • ハードウェアとアーキテクチャ
  • 安全性、リスク、信頼性、品質管理

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