Asynchronous stochastic decoding of low-density parity-check codes

Naoya Onizawa, Vincent C. Gaudet, Takahiro Hanyu, Warren J. Gross

研究成果: Conference contribution

10 被引用数 (Scopus)

抄録

This paper presents an asynchronous scheduling algorithm for high-throughput stochastic low-density parity-check (LDPC) decoders. Stochastic computation provides ultra-low-complexity hardware and can be implemented using binary or multiple-valued logic gates. Using asynchronous control, it also eliminates a global clock signal and therefore eases the worst-case timing restrictions. A timing model of asynchronous-computation behaviours under a 90nm CMOS technology is used to demonstrate that the proposed algorithm with an optimized computation delay properly decodes a regular (1024, 512) LDPC code without the "lock-up" problem that potentially stops decoding before convergence and hence causes loss in coding gain. Based on our models, the proposed scheme achieves up to 7.37x improvement in decoding throughput with comparable BER performance in comparison with performance results of a conventional synchronous stochastic decoder.

本文言語English
ホスト出版物のタイトルProceedings - IEEE 42nd International Symposium on Multiple-Valued Logic, ISMVL 2012
ページ92-97
ページ数6
DOI
出版ステータスPublished - 2012
イベント42nd IEEE International Symposium on Multiple-Valued Logic, ISMVL 2012 - Victoria, BC, Canada
継続期間: 2012 5 142012 5 16

出版物シリーズ

名前Proceedings of The International Symposium on Multiple-Valued Logic
ISSN(印刷版)0195-623X

Other

Other42nd IEEE International Symposium on Multiple-Valued Logic, ISMVL 2012
国/地域Canada
CityVictoria, BC
Period12/5/1412/5/16

ASJC Scopus subject areas

  • コンピュータ サイエンス(全般)
  • 数学 (全般)

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