Area-efficient LUT circuit design based on asymmetry of MTJ's current switching for a nonvolatile FPGA

研究成果: Conference contribution

13 被引用数 (Scopus)

抄録

A compact lookup table (LUT) circuit using spin transfer-torque magnetic tunnel junction (STT-MTJ) devices combined with MOS transistors is proposed for a standby-power-free field-programmable gate array (FPGA). Since STT-MTJ devices essentially have an asymmetric characteristic in switching currents, one of two write-control transistors can be implemented with a small feature size, while the width of the other one is still large. By sharing the large size of write-control transistor, almost all the transistor size in the proposed LUT circuit becomes small. In fact, the effective silicon area of the proposed write-control transistors for a 6-input LUT circuit is reduced to 68 % in comparison with that of a conventional nonvolatile LUT circuit without applying the asymmetric transistor sizing.

本文言語English
ホスト出版物のタイトル2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012
ページ334-337
ページ数4
DOI
出版ステータスPublished - 2012 10 16
イベント2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012 - Boise, ID, United States
継続期間: 2012 8 52012 8 8

出版物シリーズ

名前Midwest Symposium on Circuits and Systems
ISSN(印刷版)1548-3746

Other

Other2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012
国/地域United States
CityBoise, ID
Period12/8/512/8/8

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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