抄録

Code search problems refer to searching a particular bit pattern that satisfies given constraints. Obtaining such codes is very important in fields such as data encoding, error correcting, cryptography, etc. Unfortunately, the search time increases exponentially with the number of bits in the code, and typically requires many months of computation to find large codes. On the other hand, the search method mostly consists of 1-bit computations, so that reconfigurable hardware such as FPGAs (field programmable gate arrays) can be used to successfully obtain a massive degree of parallelism. In this paper, we propose a heterogeneous system with a CPU and an FPGA to speed-up code search problems. According to the evaluation, we obtain over 86 times speed-up compared to typical CPU-based implementation for extremal doubly even self-dual code search problem of length 128.

本文言語English
ホスト出版物のタイトルSupercomputing Frontiers - 4th Asian Conference, SCFA 2018, Proceedings
編集者Rio Yokota, Weigang Wu
出版社Springer Verlag
ページ146-155
ページ数10
ISBN(印刷版)9783319699523
DOI
出版ステータスPublished - 2018
イベント4th Asian Conference on Supercomputing Frontiers, SCFA 2018 - Singapore, Singapore
継続期間: 2018 3 262018 3 29

出版物シリーズ

名前Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
10776 LNCS
ISSN(印刷版)0302-9743
ISSN(電子版)1611-3349

Other

Other4th Asian Conference on Supercomputing Frontiers, SCFA 2018
CountrySingapore
CitySingapore
Period18/3/2618/3/29

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

フィンガープリント 「Architecture of an FPGA-based heterogeneous system for code-search problems」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル