Architecture of a low-power FPGA based on self-adaptive voltage control

Shota Ishihara, Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama

研究成果: Conference contribution

6 被引用数 (Scopus)

抄録

This paper presents a low-power FPGA with multiple supply voltages. In the proposed FPGA, the supply voltage of each logic block is self-adaptive to the workload, data path and temperature to minimize the power consumption without system performance degradation. In the self-adaptive voltage control scheme, features of the asynchronous architecture are exploited. The data arrival of the asynchronous architecture can be easily detected by detecting the change of the data's phase. By exploiting this feature, the critical path can be detected in real time. Logic blocks on the non-critical path are autonomously switched to a lower supply voltage to reduce the power consumption.

本文言語English
ホスト出版物のタイトル2009 International SoC Design Conference, ISOCC 2009
ページ274-277
ページ数4
DOI
出版ステータスPublished - 2009 12 1
イベント2009 International SoC Design Conference, ISOCC 2009 - Busan, Korea, Republic of
継続期間: 2009 11 222009 11 24

出版物シリーズ

名前2009 International SoC Design Conference, ISOCC 2009

Other

Other2009 International SoC Design Conference, ISOCC 2009
CountryKorea, Republic of
CityBusan
Period09/11/2209/11/24

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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