Architecture and implementation of an associative memory using sparse clustered networks

Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Warren J. Gross

研究成果: Paper査読

23 被引用数 (Scopus)

抄録

Associative memories are alternatives to indexed memories that when implemented in hardware can benefit many applications such as data mining. The classical neural network based methodology is impractical to implement since in order to increase the size of the memory, the number of information bits stored per memory bit (efficiency) approaches zero. In addition, the length of a message to be stored and retrieved needs to be the same size as the number of nodes in the network causing the total number of messages the network is capable of storing (diversity) to be limited. Recently, a novel algorithm based on sparse clustered neural networks has been proposed that achieves nearly optimal efficiency and large diversity. In this paper, a proof-of-concept hardware implementation of these networks is presented. The limitations and possible future research areas are discussed.

本文言語English
ページ2901-2904
ページ数4
DOI
出版ステータスPublished - 2012
外部発表はい
イベント2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of
継続期間: 2012 5 202012 5 23

Other

Other2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
国/地域Korea, Republic of
CitySeoul
Period12/5/2012/5/23

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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