Analysis of GOI-MOSFET with high-k gate dielectric and metal gate fabricated by Ge condensation technique

Mungi Park, Jicheol Bea, Takafumi Fukushima, Mitsumasa Koyanagi

研究成果: Article査読

1 被引用数 (Scopus)


In order to improve the complementary metal-oxide-semiconductor (CMOS) circuit performance under sub-100 nm technology nodes with low supply voltages, a metal-oxide-semiconductor field-effect transistor (MOSFET) including a high mobility channel and a silicon-on-insulator (SOI) structure is a promising device design. According to The International Technology Roadmap for Semiconductors (ITRS), a 25-nm MOSFET with a gate oxide equivalent oxide thickness (EOT) of 5-8 nm will be produced by 2010. Several groups have reported thermally stable gate dielectrics such as HfO2, ZrO2, Hf2Si1-x, HfOxNy, ZrO xNy, and Ln2O3. However, considering the relatively thick interfacial layer (∼0.5 nm SiOx) and the relatively low dielectric constant (10-20) of these materials, it is very difficult to scale down the EOT below 1 nm. In this paper, we report on the electrical characteristics of sputtered HfO2 with an EOT of 0.78 nm. We report Ge metal-insulator-semiconductor field-effect transistors (MISFETs) with HfO2+ and W/W2N metal gate electrode on germanium-on-insulator (GOI) wafer obtained by the new graded Ge condensation method. Excellent device characteristics are achieved with a subthreshold swing of 80 mV/dec and low gate leakage.

ジャーナルSurface and Interface Analysis
出版ステータスPublished - 2006 12 1

ASJC Scopus subject areas

  • Chemistry(all)
  • Condensed Matter Physics
  • Surfaces and Interfaces
  • Surfaces, Coatings and Films
  • Materials Chemistry

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