This paper describes analysis of on-chip bus power in the presence of arrival time variations of input signals. With shrinking process geometries, coupling power between neighboring bus lines has enlarged. The coupling power depends on not only signal transition type but also the relative signal transition time difference. For conventional dynamic power estimation, deterministic models of the time difference are assumed. We deal with nondeterministic models considering variations, because variations such as process variations cause the input arrival time variations. As a result of the time variations, power estimation error may increase. In our analysis and experiments, firstly impact of the time variations on the power consumption is analytically modeled. Then, it is demonstrated that certain types of bus coding techniques suppress the impact.
|ジャーナル||Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)|
|出版ステータス||Published - 2009 3 11|
|イベント||18th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2008 - Lisbon, Portugal|
継続期間: 2008 9 10 → 2008 9 12
ASJC Scopus subject areas
- Theoretical Computer Science
- Computer Science(all)