Analog CMOS implementation of quantized interconnection neural networks for memorizing limit cycles

Cheol Young Park, Koji Nakajima

研究成果: Article査読

2 被引用数 (Scopus)

抄録

In order to investigate the dynamic behavior of quantized interconnection neural networks on neuro-chips, we have designed and fabricated hardware neural networks according to design rule of a 1. 2 μm CMOS technology. To this end, we have developed programmable synaptic weights for the interconnection with three values of ±1 and 0. We have tested the chip and verified the dynamic behavior of the networks in a circuit level. As a result of our study, we can provide the most straightforward application of networks for a dynamic pattern classifier. The proposed network is advantageous in that it does not need extra exemplar to classify shifted or reversed patterns.

本文言語English
ページ(範囲)952-957
ページ数6
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E82-A
6
出版ステータスPublished - 1999
外部発表はい

ASJC Scopus subject areas

  • 信号処理
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学
  • 応用数学

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