In order to investigate the dynamic behavior of quantized interconnection neural networks on neuro-chips, we have designed and fabricated hardware neural networks according to design rule of a 1. 2 μm CMOS technology. To this end, we have developed programmable synaptic weights for the interconnection with three values of ±1 and 0. We have tested the chip and verified the dynamic behavior of the networks in a circuit level. As a result of our study, we can provide the most straightforward application of networks for a dynamic pattern classifier. The proposed network is advantageous in that it does not need extra exemplar to classify shifted or reversed patterns.
|ジャーナル||IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences|
|出版ステータス||Published - 1999 1 1|
ASJC Scopus subject areas
- Signal Processing
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering
- Applied Mathematics