An operand status based instruction steering scheme for clustered architectures

Yukinori Sato, Kenichi Suzuki, Tadao Nakamura

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

Clustered architectures which intend to process data within a localized PE are one of the approaches to increase the performance under the difficulties of the wire delay problems. The performance of the clustered architecture depends on the implemented instruction steering scheme. Existing steering schemes insert inter-PE communications to achieve load balance among PEs. These insertions delay the executions of the dependent instructions and lead to the degradation of the performance. In this paper, we propose a novel instruction steering scheme, which gives priority to critical dependencies. The way to find out the critical dependencies is by observing the status of the source operands of an instruction. We evaluate the proposed scheme and compare it with the existing ones. The results show that the proposed scheme outperforms the existing schemes in terms of instruction per clock because of reductions of the critical inter-PE communications with superior load balance among the PEs.

本文言語English
ホスト出版物のタイトルProceedings of the 2005 International Conference on Computer Design, CDES'05
ページ168-174
ページ数7
出版ステータスPublished - 2005 12月 1
イベント2005 International Conference on Computer Design, CDES'05 - Las Vegas, NV, United States
継続期間: 2005 6月 272005 6月 30

出版物シリーズ

名前Proceedings of the 2005 International Conference on Computer Design, CDES'05

Other

Other2005 International Conference on Computer Design, CDES'05
国/地域United States
CityLas Vegas, NV
Period05/6/2705/6/30

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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