A nonvolatile associative memory architecture based on the Magnetic Tunnel Junction (MTJ) devices has been proposed for high-speed low-power recognition. In order to reduce the power dissipation without sacrificing the speed performance, an intelligent power-saving scheme has been developed taking the advantage of non-volatility of MTJ devices. The power lines of 4-Transistor 2-MTJ nonvolatile memory cells are controlled by not only word line signals but also the internal power control signals supplied from the data-mask/power-gating units to only activate the currently accessed memory elements. The proof-of-concept chip for 128-dimension data vectors has been designed under a 90-nm 5-metal CMOS/MTJ hybrid technology, and the chip operation at 100MHz has been verified by SPICE simulation. Compared to the conventional 6T-SRAM architecture, the proposed architecture achieves the higher speed and up to 97% power reduction. Moreover, this architecture is also proved to be particularly suitable for the applications with higher dimension data vectors.