An impact of circuit scale on the performance of 3-D stacked arithmetic units

Jubee Tada, Ryusuke Egawa, Hiroaki Kobayashi

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

Recently, the 3-D stacked integrated circuit technology has been expected to overcome the limitations in the design of the 2-D implemented microprocessors. This paper examines the potential of 3-D integration in design and implementation of large-scale arithmetic units. In this paper, 3-D stacked parallel multipliers with various operand sizes are designed, and the effect of circuit scale on the performance of 3-D stacked multipliers is discussed. In the design of a large-scale parallel multiplier, a lot of through-silicon-vias are required by the conventional partitioning pattern. This paper proposes a partitioning pattern suitable for a large-scale 3-D stacked parallel multiplier. The proposed partitioning pattern aims to reduce the number of TSVs with a large-scale parallel multiplier. Based on the proposed partitioning pattern, 3-D stacked 32, 64, and 128-bit multipliers are designed and evaluated. The proposed partitioning pattern achieves a 13.4% reduction in critical path delay and a 10.4% reduction in power consumption compared to the 2-D implementation, in the case of an 128-bit four-layer implemented 3-D stacked multiplier.

本文言語English
ホスト出版物のタイトル2014 International 3D Systems Integration Conference, 3DIC 2014 - Proceedings
出版社Institute of Electrical and Electronics Engineers Inc.
ISBN(電子版)9781479984725
DOI
出版ステータスPublished - 2014 1 1
イベントInternational 3D Systems Integration Conference, 3DIC 2014 - Kinsdale, Ireland
継続期間: 2014 12 12014 12 3

出版物シリーズ

名前2014 International 3D Systems Integration Conference, 3DIC 2014 - Proceedings

Other

OtherInternational 3D Systems Integration Conference, 3DIC 2014
国/地域Ireland
CityKinsdale
Period14/12/114/12/3

ASJC Scopus subject areas

  • 電子工学および電気工学
  • 電子材料、光学材料、および磁性材料
  • ハードウェアとアーキテクチャ

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