An Experimental 2-bit/Cell Storage DRAM for Macroce11 or Memory-on-Logic Application

Tohru Furuyama, Takashi Ohsawa, Yohji Watanabe, Kazuyoshi Muraoka, Kenji Natori, Yousei Nagahama, Tohru Kimura, Hiroto Tanaka

    研究成果: Article査読

    17 被引用数 (Scopus)

    抄録

    A novel 2-bit (four-level)/cell storage technique is described. This technique saves the RAM area, in particular the cell array area which is highly defect sensitive provides fairly fast access time. An experimental 1-Mbit DRAM has been fabricated and has successfully demon-strated the feasibility of this technique for embedded memory applications.

    本文言語English
    ページ(範囲)388-393
    ページ数6
    ジャーナルIEEE Journal of Solid-State Circuits
    24
    2
    DOI
    出版ステータスPublished - 1989 4

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

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