An Experimental 16-Mbit CMOS DRAM Chip with a 100-MHz Serial READ/WRITE Mode

Shigeyoshi Watanabe, Yukihito Oowak, Yasuo Itoh, Koji Sakui, Kenji Numata, Tsuneaki Fuse, Takayuki Kobayashi, Kenji Tsuchida, Masahiko Chiba, Takahiko Hara, Masako Ohta, Fumio Horiguch, Katsuhiko Hieda, Akihiro Nitayama, Takeshi Hamamoto, Kazunori Ohuchi, Fujio Masuoka

研究成果: Article査読

3 被引用数 (Scopus)


A 5-V 4M word x 4-bit dynamic RAM with a 100-MHz serial READ/WRITE mode has been designed and fabricated using 0.7-ism triple-tub CMOS technology. The RAM utilizes a newly developed STT (STacked Trench capacitor) cell which achieved 37 fF in a small cell size of 1.7x 3.6 m2. The STD (Sidewall Transistor with Double doped drain) structure has been introduced for PMOSFET's to realize high-speed operation, and in order to ensure the MOSFET reliability the 5-V external supply voltage is converted to a 4-V internal supply voltage by an on-chip voltage converter circuit. A new on-chip interleaved circuit and double-input-buffer scheme have been introduced to realize a high-speed serial READ/WRITE operation. Using an external 5-V power supply, the RAM achieved a 100-MHz serial access cycle, and the RA S access time is 70 ns. The typical active current is 120 mA at a 190-ns cycle time.

ジャーナルIEEE Journal of Solid-State Circuits
出版ステータスPublished - 1989 6

ASJC Scopus subject areas

  • 電子工学および電気工学


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