An energy-aware set-level refreshing mechanism for eDRAM last-level caches

Masayuki Sato, Zehua Li, Ryusuke Egawa, Hiroaki Kobayashi

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

Since embedded DRAM (eDRAM) has a higher density with a lower leakage power than SRAM, it is promising to be used as the last-level cache (LLC) of a microprocessor. However, an eDRAM LLC needs a high energy consumption for refresh operations. In particular, the conventional eDRAM LLC refreshes even dead cache lines that are not reused until their evictions. This paper proposes an energy-aware set-level refreshing mechanism to reduce the wasted energy due to unnecessary refreshes of dead cache lines. In the case where the cache resources are excessive compared with the demand of an application, the excessive resources are wasted to store dead lines. Therefore, the proposed mechanism dynamically adjusts the number of refreshed cache lines. The evaluation results show that the proposed mechanism can reduce the LLC energy consumption by 46% with a 1% performance loss on average.

本文言語English
ホスト出版物のタイトル21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 - Proceedings
出版社Institute of Electrical and Electronics Engineers Inc.
ページ1-3
ページ数3
ISBN(電子版)9781538661024
DOI
出版ステータスPublished - 2018 6 5
イベント21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 - Yokohama, Japan
継続期間: 2018 4 182018 4 20

出版物シリーズ

名前21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 - Proceedings

Other

Other21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018
国/地域Japan
CityYokohama
Period18/4/1818/4/20

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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