In this paper, an electrostatic-discharge (ESD) protection device for RF complementary metal oxide semiconductor (CMOS) ICs utilizing the Depletion-layer-Extended Transistor (DET) is reported. The DET, which reduces the area component of junction capacitance by about 1/3, realizes an ESD protection device with low parasitic capacitance. With transmission line pulse (TLP) testing, the DET demonstrates about the same or higher ESD robustness than the conventional transistor. The junction capacitance of the proposed device for obtaining a failure current (It2) of 1-1.33 A in TLP testing, corresponding to a Human Body Model (HBM) tolerance of 2 kV, is estimated to be very low, less than 150 fF. The proposed ESD protection device is very promising for the realization of high-performance and highly reliable RF CMOS ICs.
|ジャーナル||Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers|
|出版ステータス||Published - 2003 4月|
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