An electrostatic-discharge (ESD) protection device with low parasitic capacitance utilizing a depletion-layer-extended transistor (DET) for RF CMOS ICs

Takahiro Ohnakado, Satoshi Yamakawa, Akihiko Furukawa, Kazuyasu Nishikawa, Takaaki Murakami, Yasushi Hashizume, Kazuyuki Sugahara, Jun Tomisawa, Noriharu Suematsu, Tatsuo Oomori

研究成果: Article査読

抄録

In this paper, an electrostatic-discharge (ESD) protection device for RF complementary metal oxide semiconductor (CMOS) ICs utilizing the Depletion-layer-Extended Transistor (DET) is reported. The DET, which reduces the area component of junction capacitance by about 1/3, realizes an ESD protection device with low parasitic capacitance. With transmission line pulse (TLP) testing, the DET demonstrates about the same or higher ESD robustness than the conventional transistor. The junction capacitance of the proposed device for obtaining a failure current (It2) of 1-1.33 A in TLP testing, corresponding to a Human Body Model (HBM) tolerance of 2 kV, is estimated to be very low, less than 150 fF. The proposed ESD protection device is very promising for the realization of high-performance and highly reliable RF CMOS ICs.

本文言語English
ページ(範囲)2077-2081
ページ数5
ジャーナルJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
42
4 B
DOI
出版ステータスPublished - 2003 4月
外部発表はい

ASJC Scopus subject areas

  • 工学(全般)
  • 物理学および天文学(全般)

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