An efficient approach to verifying galois-field arithmetic circuits of higher degrees and its application to ECC decoders

Rei Ueno, Kotaro Okamoto, Naofumi Hommam, Takafumi Aoki

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

This paper presents an efficient approach to verifying higher-degree Galois-Field(GF) arithmetic circuits. The proposed method describes GF arithmetic circuits by graph-based representation, and verifies them by a combination of algebraic method with a new verification method based on natural deduction for the first-order predicate logic with equal sign. The natural deduction method can verify kind of higher-degree GF arithmetic circuits efficiently while the conventional methods requires enormous time to verify them or sometimes cannot verify them. In this paper, we apply the proposed method to the design and verifications of various Reed-Solomon (RS) code decoders. We confirm that the proposed method can verify RS code decoders with higher-degree functions while the conventional method fails. In particular, we show that the proposed method can be applied to practical decoders with 8-bit symbols.

本文言語English
ホスト出版物のタイトルProceedings - 2014 IEEE 44th International Symposium on Multiple-Valued Logic, ISMVL 2014
出版社IEEE Computer Society
ページ144-149
ページ数6
ISBN(印刷版)9781479935345
DOI
出版ステータスPublished - 2014
イベント44th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2014 - Bremen, Germany
継続期間: 2014 5 192014 5 21

出版物シリーズ

名前Proceedings of The International Symposium on Multiple-Valued Logic
ISSN(印刷版)0195-623X

Other

Other44th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2014
CountryGermany
CityBremen
Period14/5/1914/5/21

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

フィンガープリント 「An efficient approach to verifying galois-field arithmetic circuits of higher degrees and its application to ECC decoders」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル