An ASIC implementation of phase correlation based on run-time reconfiguration technique

Naoto Miyamoto, Katsuhiko Hanzawa, Tadahiro Ohmi

研究成果: Conference contribution

抄録

In this paper, we present an application-specific LSI that is designed using a run-time reconfiguration technique. The implemented algorithm is phase correlation. The calculation of phase correlation includes Fast Fourier Transform (FFT) followed by Inverse Fast Fourier Transform (IFFT). We have developed a dual-decimation butterfly module that can be self-reconfigured, at run-time, to be either decimation-in-time (DIT) or decimation-in-frequency (DIF). By sharing the common parts between the DIT and DIF butterfly modules, the dual-decimation butterfly module can reduce the logic size to about half. DIT-mode is used for FFT and DIF-mode is used for IFFT. No data reordering, such as natural-to-reverse or reverse-to-natural conversion, between FFT and IFFT is necessary. As a consequence, the amount of intermediate frame buffers and the number of memory accesses are significantly reduced.

本文言語English
ホスト出版物のタイトルProceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09
ページ308-311
ページ数4
DOI
出版ステータスPublished - 2009 12 1
イベント2009 International Conference on Field-Programmable Technology, FPT'09 - Sydney, Australia
継続期間: 2009 12 92009 12 11

出版物シリーズ

名前Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09

Other

Other2009 International Conference on Field-Programmable Technology, FPT'09
国/地域Australia
CitySydney
Period09/12/909/12/11

ASJC Scopus subject areas

  • 計算理論と計算数学
  • ハードウェアとアーキテクチャ
  • ソフトウェア

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