An area-efficient multiple-valued reconfigurable vlsi architecture using an x-net

Xu Bai, Michitaka Kameyama

研究成果: Conference contribution

3 被引用数 (Scopus)

抄録

An X-net is employed for simplifying interconnections and switch blocks of a multiple-valued reconfigurable VLSI (MV-RVLSI). One cell composed of a logic block and a switch block is connected to four adjacent 'X' intersections by four one-bit switches. A multiple-valued X-net data transfer scheme is proposed to improve the utilization of the X-net, where two binary data can be transferred from two adjacent cells to one common adjacent cell simultaneously at each 'X' intersection. To evaluate the MV-RVLSIs, a sum-of-absolute-differences operation is mapped onto a previous MV-RVLSI using an 8 nearest-neighbor mesh network (8-NNM) and the MV-RVLSI using the X-net, respectively. The area of the MV-RVLSI based on the multiple-valued X-net data transfer scheme is reduced to 73% and 84%, respectively, in comparison with those of the MVRVLSI using the 8-NNM and the MV-RVLSI based on a binary X-net data transfer scheme.

本文言語English
ホスト出版物のタイトルProceedings - 2013 IEEE 43rd International Symposium on Multiple-Valued Logic, ISMVL 2013
ページ272-277
ページ数6
DOI
出版ステータスPublished - 2013
イベント2013 IEEE 43rd International Symposium on Multiple-Valued Logic, ISMVL 2013 - Toyama, Japan
継続期間: 2013 5 222013 5 24

出版物シリーズ

名前Proceedings of The International Symposium on Multiple-Valued Logic
ISSN(印刷版)0195-623X

Other

Other2013 IEEE 43rd International Symposium on Multiple-Valued Logic, ISMVL 2013
国/地域Japan
CityToyama
Period13/5/2213/5/24

ASJC Scopus subject areas

  • コンピュータ サイエンス(全般)
  • 数学 (全般)

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