An architecture of small-scaled neuro-hardware using probabilistically coded pulse neurons

Takeshi Kawashima, Akio Ishiguro, Shigeru Okuma

研究成果: Article査読

3 被引用数 (Scopus)

抄録

In this paper, we present an architecture for neuro-hardware that can be realized in circuits of far smaller scale than in the conventional approach. In order to reduce the scale of the circuits, the architecture employs a new method of computing the membrane potential and the sigmoidal function by encapsulating the probabilistic properties into the relative delay between two pulses. The proposed architecture makes it possible to integrate more than 100 neurons in the latest FPGA chip, which is a 13-fold miniaturization compared to the conventional architecture.

本文言語English
ページ(範囲)48-55
ページ数8
ジャーナルElectrical Engineering in Japan (English translation of Denki Gakkai Ronbunshi)
139
4
DOI
出版ステータスPublished - 2002 1 1
外部発表はい

ASJC Scopus subject areas

  • Energy Engineering and Power Technology
  • Electrical and Electronic Engineering

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