TY - GEN
T1 - An architecture of small-scaled neuro-hardware using probabilistically-coded pulse neurons
AU - Kawashima, T.
AU - Ishiguro, A.
AU - Okuma, S.
PY - 2000/1/1
Y1 - 2000/1/1
N2 - We present an architecture of a neuro-hardware that can be realized on a small-scaled circuit compared to the conventional approach. In order to reduce the scale of the circuits, the architecture employs a new method of computing the membrane potential and sigmoid function by encapsulating the probability properties into relative delay between two pulses. The proposed architecture enables one to integrate more than one hundred of neurons on a latest FPGA chip, which means thirteen-fold miniaturization compared to the conventional architecture.
AB - We present an architecture of a neuro-hardware that can be realized on a small-scaled circuit compared to the conventional approach. In order to reduce the scale of the circuits, the architecture employs a new method of computing the membrane potential and sigmoid function by encapsulating the probability properties into relative delay between two pulses. The proposed architecture enables one to integrate more than one hundred of neurons on a latest FPGA chip, which means thirteen-fold miniaturization compared to the conventional architecture.
UR - http://www.scopus.com/inward/record.url?scp=84969135207&partnerID=8YFLogxK
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U2 - 10.1109/IECON.2000.973227
DO - 10.1109/IECON.2000.973227
M3 - Conference contribution
AN - SCOPUS:84969135207
T3 - IECON Proceedings (Industrial Electronics Conference)
SP - 657
EP - 663
BT - IECON Proceedings (Industrial Electronics Conference)
PB - IEEE Computer Society
ER -