This article proposed an architecture of a neuro-hardware that can be realized on by far a small-scaled circuit compared to the conventional approach. In order to reduce the scale of the circuits, the architecture employs a new method of computing the membrane potential and the sigmoidal function by encapsulating the probability properties into relative delay between two pulses of the different signal lines. Proposed architecture enables to integrate more than one hundred of neurons on a latest FPGA chip, which means thirteen-fold miniaturization compared to conventional architecture.
|ジャーナル||Proceedings of the IEEE International Conference on Systems, Man and Cybernetics|
|出版ステータス||Published - 2001 1 1|
ASJC Scopus subject areas
- Control and Systems Engineering
- Hardware and Architecture