Spin-Transfer Torque RAM (STT-RAM) has attracted attention as a key element for the Last-Level Cache (LLC) of a future microprocessor. Since STT-RAM has a higher density than SRAM and non-volatility, STT-RAM can contribute to building the cache memory with a larger capacity and a less static energy. However, since STT-RAM changes its magnetization state in the case when storing data, the energy cost of write access requests for an STT-RAM LLC is more expensive than that of an SRAM LLC. As a result, the total energy consumption of the STT-RAM LLC for write-intensive applications may increase. To solve this problem, this paper proposes an Adjacent-Line-Merging Writeback Scheme. Since a larger cache line of an STT-RAM cache can contribute to the reduction in the write energy cost per byte, the upper-level cache merges two adjacent small lines to one large line, and then writes the merged line back to the STT-RAM LLC. Moreover, the larger line size for the LLC leads to a reduction in the static energy cost. The evaluation results show that the proposed scheme can reduce the energy consumption of the STT-RAM LLC by up to 26, and 9.3 percent on average.
|ジャーナル||IEEE Transactions on Multi-Scale Computing Systems|
|出版ステータス||Published - 2018 10 1|
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