AES S-Box Hardware with Efficiency Improvement Based on Linear Mapping Optimization

Ayano Nakashima, Rei Ueno, Naofumi Homma

研究成果: Article査読

抄録

This paper presents a new Advanced Encryption Standard (AES) S-Box hardware design based on linear mappings optimized by combining multiplicative and exponential offsets. Generally, the performance of S-Box with composite field representations depends on the structure of linear mappings (i.e., transformation matrices) between the polynomial field and composite field before and after the S-Box. So far, multiplicative and exponential offsets have been applied only to Boyar-Peralta type S-Box variants for optimizing the transformation matrix. In this study, we apply the offset methods to another S-Box based on the redundant Galois field arithmetic and evaluate the performance by logic synthesis. Specifically, we design and evaluate two new types of S-Box hardware: one for encryption only (ENC) and the other for both encryption and decryption (ENC/DEC). The evaluation result confirms that the proposed ENC and ENC/DEC S-Boxes achieve a performance up to 8.7% and 28.8% higher, respectively, than the highest-performing conventional ones in terms of the area timing (AT) product.

本文言語English
ページ(範囲)1
ページ数1
ジャーナルIEEE Transactions on Circuits and Systems II: Express Briefs
DOI
出版ステータスAccepted/In press - 2022

ASJC Scopus subject areas

  • 電子工学および電気工学

フィンガープリント

「AES S-Box Hardware with Efficiency Improvement Based on Linear Mapping Optimization」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル