Advanced FinFET process technology for 20 nm node and beyond

M. Masahara, T. Matsukawa, K. Endo, Y. X. Liu, W. Mizubayashi, S. Migita, S. O'Uchi, H. Ota, Y. Morita

研究成果: Conference contribution

7 被引用数 (Scopus)

抄録

One of the biggest challenges for the VLSI circuits with 20-nm-technology nodes and beyond is to overcome the issue of a catastrophic increase in power dissipation of the circuit due to short channel effects (SCEs). Fortunately, double-gate FinFETs have a promising potential to overcome this issue due to their superior SCE immunity even with an undoped channel thanks to the 3D structure. This paper presents novel FinFET process technologies for 20 nm node and beyond.

本文言語English
ホスト出版物のタイトル4th IEEE International NanoElectronics Conference, INEC 2011
DOI
出版ステータスPublished - 2011 9月 26
外部発表はい
イベント4th IEEE International Nanoelectronics Conference, INEC 2011 - Tao-Yuan, Taiwan, Province of China
継続期間: 2011 6月 212011 6月 24

出版物シリーズ

名前Proceedings - International NanoElectronics Conference, INEC
ISSN(印刷版)2159-3523

Other

Other4th IEEE International Nanoelectronics Conference, INEC 2011
国/地域Taiwan, Province of China
CityTao-Yuan
Period11/6/2111/6/24

ASJC Scopus subject areas

  • 電子工学および電気工学

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