Accurate error bit mode analysis of STT-MRAM chip with a novel current measurement module implemented to gigabit class memory test system

R. Tamura, I. Mori, N. Watanabe, H. Koike, T. Endoh

研究成果: Conference contribution

抄録

A novel memory test system is needed for future STTMRAM mass production that supports error bit analysis and its mode categorization on STT-MRAM chip measurement, as STTMRAM cell's switching is a probabilistic phenomenon based on quantum mechanics. In order to meet this requirement, we successfully developed a novel current measurement module on gigabit class memory test system that can measure the time domain switching current of each bit with nanosecond and microampere resolution. Moreover, we demonstrated the world's first results that our developed memory test system detects all error bits in fabricated STT-MRAM chip and categorizes error bit mode according to the switching characteristics of each error bit. This novel memory test system with the function of accurate and high speed time domain current measurement on the same level as single bit measurement equipment is expected to accelerate RD and mass production of STT-MRAM and other applications such as ReRAM and PCM.

本文言語English
ホスト出版物のタイトルNVMTS 2018 - Non-Volatile Memory Technology Symposium 2018
出版社Institute of Electrical and Electronics Engineers Inc.
ISBN(電子版)9781538677834
DOI
出版ステータスPublished - 2019 1 4
イベント18th Non-Volatile Memory Technology Symposium, NVMTS 2018 - Sendai, Japan
継続期間: 2018 10 222018 10 24

出版物シリーズ

名前NVMTS 2018 - Non-Volatile Memory Technology Symposium 2018

Conference

Conference18th Non-Volatile Memory Technology Symposium, NVMTS 2018
国/地域Japan
CitySendai
Period18/10/2218/10/24

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学
  • 安全性、リスク、信頼性、品質管理

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