Accurate circuit performance prediction model and lifetime prediction method of NBT stressed devices for highly reliable ULSI circuits

An accurate circuit level prediction model for predicting performance degradation due to negative bias temperature (NET) stress and a device lifetime prediction method are proposed in this paper. The proposed model consists of a threshold voltage (V_th) shift and a drain current (I_D) reducticn models. The developed models are incorporated into a compact MOSFET model so that we can directly link the device electrical degradation to the circuit simulation. The validity of the developed models is confirmed by the experimental results of I-V characteristics of pMOSFET before and after stress. Then, the circuit performance prediction is carried out for a 199-stage ring oscillator on its waveform and oscillation frequency. Excellent agreements between experimental results and predicted results are obtained. Since only a suitable acceleration method allows us to develop the accurate models, the new negative bias temperature instability (NBTI) acceleration method using cold-holes is also developed. Filially, we demonstrate the accurate NBTI lifetime prediction using the method.