Accurate and high-speed asynchronous network-on-chip simulation using physical wire-delay information

Takahiro Hanyu, Yuma Watanabe, Atsushi Matsumoto

研究成果: Conference contribution

3 被引用数 (Scopus)

抄録

A performance-evaluation simulator is a key tool for exploring appropriate asynchronous Network-on-Chip (NoC) architecture in early stage of LSI design. This paper presents a highly accurate performance-evaluation simulator with maintaining a short evaluation time for designing a high-performance asynchronous NoC. The use of a precise asynchronous-router circuit model, whose physical parameters such as wire delays as well as unit gate delays are preliminarily obtained using LSI CAD tool, makes it accurate to simulate asynchronous NoC systems. As a design example, multi-core asynchronous mesh-structured NoC systems are simulated by both the previous method and the proposed one whose results, such as latency and throughput, are validated with a highly precise transistor-level simulation result. As a result, the proposed simulator achieves almost the same accuracy as the corresponding gate-level simulators, while its simulation speed is one-thousand-times faster than that of the gate-level one at the packet injection rate of 30 (packets/sec).

本文言語English
ホスト出版物のタイトルProceedings - 2013 IEEE 43rd International Symposium on Multiple-Valued Logic, ISMVL 2013
ページ266-271
ページ数6
DOI
出版ステータスPublished - 2013 8月 1
イベント2013 IEEE 43rd International Symposium on Multiple-Valued Logic, ISMVL 2013 - Toyama, Japan
継続期間: 2013 5月 222013 5月 24

出版物シリーズ

名前Proceedings of The International Symposium on Multiple-Valued Logic
ISSN(印刷版)0195-623X

Other

Other2013 IEEE 43rd International Symposium on Multiple-Valued Logic, ISMVL 2013
国/地域Japan
CityToyama
Period13/5/2213/5/24

ASJC Scopus subject areas

  • コンピュータ サイエンス(全般)
  • 数学 (全般)

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