A WiMAX turbo decoder with tailbiting BIP architecture

Hiroaki Arai, Naoto Miyamoto, Koji Kotani, Hisanori Fujisawa, Takashi Itoh

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

In this paper, a tailbitlng block-interleaved pipelining (BIP) architecture is proposed for high-throughput and energy efficient WiMAX turbo decoders. Conventional sliding window (SW) BIP turbo decoders suffer from many warm-up calculations and large memory size when the number of pipeline stages is Increased. Instead of the SW, we combined the tailbltlng method with BIP. Consequently, more than 50% of the warm-up calculation was reduced, and necessary memory size became constant. We have implemented a tailbiting BIP WiMAX turbo decoder with 4 pipeline stages in the area of 3.8 mm2 using a 0.18 μm CMOS technology. The chip achieves 45 Mbps/iter and 3.11 nJ/b/iter at 99 MHz operation.

本文言語English
ホスト出版物のタイトルProceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
ページ377-380
ページ数4
DOI
出版ステータスPublished - 2009 12 1
イベント2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009 - Taipei, Taiwan, Province of China
継続期間: 2009 11 162009 11 18

出版物シリーズ

名前Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009

Other

Other2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
国/地域Taiwan, Province of China
CityTaipei
Period09/11/1609/11/18

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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