A voting-based working set assessment scheme for dynamic cache resizing mechanisms

研究成果: Conference contribution

5 被引用数 (Scopus)

抄録

Considering the trade-off between performance and power consumption has become significantly important in multi-core processor design. Under this situation, one promising approach is to employ a power-aware dynamic cache partitioning mechanism. This mechanism individually manages activation of each cache way, and exclusively allocates the minimum number of required ways to each thread. In the mechanism, an appropriate number of ways for a thread is decided based on locality assessment. However, sampling results of cache accesses that are used for locality assessment are disturbed by exceptional behaviors of cache accesses, which happen in a very short period. Such sampling results may change locality assessment results to ones that are not along with the overall trend in a long access-sampling period. These assessment results will excessively adapt the cache to exceptional behaviors, and deteriorate energy efficiency. To avoid such excessive adaptation by the exceptional behaviors, this paper proposes a voting-based working set assessment scheme, in which the number of activated ways is adjusted based on majority voting of locality assessment of several short sampling periods. By using the majority voting, the proposed scheme can identify the periods including exceptional behaviors, and ignore the assessment results of these periods. As a result, the proposed scheme makes the cache resizing mechanism more stable and robust. The experimental results indicate that the proposed scheme can reduce energy consumption by up to 24%, and 10% on an average without significant performance degradation in multi-thread execution on a 2-core CMP.

本文言語English
ホスト出版物のタイトル2010 IEEE International Conference on Computer Design, ICCD 2010
ページ98-105
ページ数8
DOI
出版ステータスPublished - 2010
イベント28th IEEE International Conference on Computer Design, ICCD 2010 - Amsterdam, Netherlands
継続期間: 2010 10 32010 10 6

出版物シリーズ

名前Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
ISSN(印刷版)1063-6404

Other

Other28th IEEE International Conference on Computer Design, ICCD 2010
CountryNetherlands
CityAmsterdam
Period10/10/310/10/6

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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