A systolic memory architecture for fast codebook design based on MMPDCL algorithm

Kentaro Sano, Chiaki Takagi, Ryusuke Egawa, Kenichi Suzuki, Tadao Nakamura

研究成果: Conference contribution

5 被引用数 (Scopus)

抄録

Vector quantization with an adaptive codebook is attractive for lossy data compression. During the last few decades, architectures have been proposed to accelerate adaptive codebook design that requires a huge amount of computation. However, they are mainly based on Kohonen competitive learning algorithm or LBG algorithm that have an essential problem, the under-utilization problem. This paper presents a systolic memory architecture for high-speed codebook design based on MMPDCL algorithm not suffering from the under-utilization problem. We modify MMPDCL algorithm to exploit parallelism and implement with simple hardware. Simulation results demonstrated that the modified MMPDCL algorithm can give codebooks with comparable MSEs to the original MMPDCL algorithm.

本文言語English
ホスト出版物のタイトルInternational Conferen ON Information Technology
ホスト出版物のサブタイトルCoding Computing, ITCC 2004
編集者P.K. Srimani, A. Abraham, M. Cannataro, J. Domingo-Ferrer, R. Hashemi
ページ572-578
ページ数7
DOI
出版ステータスPublished - 2004 7 7
イベントInternational Conference on Information Technology: Coding Computing, ITCC 2004 - Las Vegas, NV, United States
継続期間: 2004 4 52004 4 7

出版物シリーズ

名前International Conference on Information Technology: Coding Computing, ITCC
1

Other

OtherInternational Conference on Information Technology: Coding Computing, ITCC 2004
国/地域United States
CityLas Vegas, NV
Period04/4/504/4/7

ASJC Scopus subject areas

  • ソフトウェア
  • 情報システム
  • 工学(全般)

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