A Systematic Design of Tamper-Resistant Galois-Field Arithmetic Circuits Based on Threshold Implementation with (d + 1) Input Shares

研究成果: Conference contribution

5 被引用数 (Scopus)

抄録

This paper presents a systematic design of tamper-resistant Galois-Field (GF) arithmetic circuits based on Threshold Implementation (TI) where a secret variable is represented withmultiple variables, called shares, given by random numbers. TI isone of the countermeasures against Differential Power Analysis(DPA) on cryptographic hardware. The security order of TIdepends on the number of shares. The minimum number ofshares to be resistant dth-order DPA is said to be (d+1). Whilethe construction of GF arithmetic circuits of quadratic functionbased on TI with (d + 1) shares is known, it is not known howto construct other types of circuits based on it. In this paper, wepresent a generalization and systematic method of constructingthe TI with (d + 1) input shares for any kind of GF arithmeticcircuit in order to design a larger variety of tamper-resistantGF arithmetic circuits. We then apply the proposed method toa cryptographic hardware design in order to demonstrate its efficiency.

本文言語English
ホスト出版物のタイトルProceedings - 2017 IEEE 47th International Symposium on Multiple-Valued Logic, ISMVL 2017
出版社IEEE Computer Society
ページ136-141
ページ数6
ISBN(電子版)9781509054954
DOI
出版ステータスPublished - 2017 6 30
イベント47th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2017 - Novi Sad, Serbia
継続期間: 2017 5 222017 5 24

出版物シリーズ

名前Proceedings of The International Symposium on Multiple-Valued Logic
ISSN(印刷版)0195-623X

Other

Other47th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2017
国/地域Serbia
CityNovi Sad
Period17/5/2217/5/24

ASJC Scopus subject areas

  • コンピュータ サイエンス(全般)
  • 数学 (全般)

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