A Systematic Design Methodology of Formally Proven Side-Channel-Resistant Cryptographic Hardware

研究成果: Article査読

抄録

This article proposes a formal design system for automatically generating provably secure register transfer level description of cryptographic hardware based on generalized masking scheme. To address the above problems, we propose a formal design and verification method for generalized masking schem (GMS)-based Galois-field (GF) arithmetic circuits. The proposed method is based on a formal approach to describing and verifying GF arithmetic circuits. The basic ideas revolve around the description of GF arithmetic circuits using a high-level mathematical graph called GF arithmetic circuit graph (GF-ACG) and its verification using an algebraic procedure based on a GroÄbner basis (GB) and a polynomial reduction technique. The proposed methodology automatically generates the GMS-based GF arithmetic circuits from circuit function and GMS order, and then its functionality is verified on the basis of GF-ACG.

本文言語English
論文番号9367223
ページ(範囲)84-92
ページ数9
ジャーナルIEEE Design and Test
38
3
DOI
出版ステータスPublished - 2021 6

ASJC Scopus subject areas

  • ソフトウェア
  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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