A switch block for multi-context FPGAs based on floating-gate-MOS functional pass-gates using multiple/binary valued hybrid signals

Shota Ishihara, Noriaki Idobata, Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama

研究成果: Article査読

1 被引用数 (Scopus)

抄録

Multi-Context Field-Programmable Gate Arrays (MC-FPGAs) provide more area-efficient implementations than conventional Field- Programmable Gate Arrays (FPGAs). In certain applications, parts of the circuit are in inactive state and there is the prospect of reconfiguring onthe- fly those parts of the circuit to execute different computations. The reconfigured parts of the circuit can share the same hardware resources by scheduling them into different time slots. However, SRAM-based Multi-Context switches (MC-switches) require a large area. To solve this problem, this paper presents an area-efficient multi-context switch block for MC-FPGAs based on floating-gate-MOS functional pass-gates using multiple/binary valued hybrid signals. By using binary-valued signals, the function of an MC-switch is divided into sub-functions such that each subfunction has only two contexts. A sub-function with two contexts is an up-literal or a down-literal. By using multiple-valued signals, each can be implemented using a single floating-gate-MOS transistor. As result, the proposed MC-switch for four contexts is implemented by only as few as two floating-gate-MOS transistors. Compared to a 32 × 32 SRAM-based multi-context switch block, the transistor count is reduced to 6.8%. The test chip for four contexts is fabricated in a 0.35μm process.

本文言語English
ページ(範囲)553-580
ページ数28
ジャーナルJournal of Multiple-Valued Logic and Soft Computing
17
5-6
出版ステータスPublished - 2011 5月 17

ASJC Scopus subject areas

  • 理論的コンピュータサイエンス
  • ソフトウェア
  • 論理

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