A Sub-10-ns 16 × 16 Multiplier Using 0.6-µm CMOS Technology

Yukihito Oowaki, Kenji Numata, Kenji Tsuchiya, Kazushi Tsuda, Hiroshi Takato, Naoko Takenouchi, Akihiro Nitayama, Shigeyoshi Watanabe, Takayuki Kobayashi, Masahiko Chiba, Akimichi Hojo, Kazunori Ohuchi

研究成果: Article査読

19 被引用数 (Scopus)

抄録

A 16×16-bit parallel multiplier fabricated in a 0.6- µm CMOS technology is described. The chip uses a modified array scheme incorporated with a Booth's algorithm to reduce the number of adding stages of partial products. The combination of scaled 0.6-µm CMOS technology and advanced arithmetic architecture achieves a multiplication time of 7.4 ns while dissipating only 400 mW. This multiplication time is shorter than other MOS high-speed multipliers previously reported and is comparable to those for advanced bipolar and GaAs multipliers.

本文言語English
ページ(範囲)762-767
ページ数6
ジャーナルIEEE Journal of Solid-State Circuits
22
5
DOI
出版ステータスPublished - 1987 10
外部発表はい

ASJC Scopus subject areas

  • 電子工学および電気工学

引用スタイル