### 抜粋

This paper presents a model-based study of SET (Single-Electron-Transistor) logic gate family for synthesizing binary and MV (Multiple-Valued) logic circuits: The use of SETs combined with MOS transistors allows a compact realization of basic logic functions that exhibit periodic transfer characteristics. These basic SET logic gates are useful for implementing binary logic circuits, MV logic circuits and binary-MV-mixed logic circuits in a highly flexible manner. As an example, this paper describes the design of various parallel counters for carry-propagation-free arithmetic, where MV signals are effectively used to achieve higher functionality with lower hardware complexity.

元の言語 | English |
---|---|

ページ（範囲） | 262-268 |

ページ数 | 7 |

ジャーナル | Proceedings of The International Symposium on Multiple-Valued Logic |

出版物ステータス | Published - 2004 7 26 |

イベント | Proceedings - 34th International Symposium on Multiple-Values Logic, ISMVL 2004 - Toronto, Ont, Canada 継続期間: 2004 5 19 → 2004 5 22 |

### ASJC Scopus subject areas

- Computer Science(all)
- Mathematics(all)

## フィンガープリント A single-electron-transistor logic gate family and its application - Part I: Basic components for binary, multiple-valued and mixed-mode logic' の研究トピックを掘り下げます。これらはともに一意のフィンガープリントを構成します。

## これを引用

*Proceedings of The International Symposium on Multiple-Valued Logic*, 262-268.