A single-electron-transistor logic gate family and its application - Part I: Basic components for binary, multiple-valued and mixed-mode logic

Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi

研究成果: Conference article

19 引用 (Scopus)

抜粋

This paper presents a model-based study of SET (Single-Electron-Transistor) logic gate family for synthesizing binary and MV (Multiple-Valued) logic circuits: The use of SETs combined with MOS transistors allows a compact realization of basic logic functions that exhibit periodic transfer characteristics. These basic SET logic gates are useful for implementing binary logic circuits, MV logic circuits and binary-MV-mixed logic circuits in a highly flexible manner. As an example, this paper describes the design of various parallel counters for carry-propagation-free arithmetic, where MV signals are effectively used to achieve higher functionality with lower hardware complexity.

元の言語English
ページ(範囲)262-268
ページ数7
ジャーナルProceedings of The International Symposium on Multiple-Valued Logic
出版物ステータスPublished - 2004 7 26
イベントProceedings - 34th International Symposium on Multiple-Values Logic, ISMVL 2004 - Toronto, Ont, Canada
継続期間: 2004 5 192004 5 22

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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