### 抜粋

This paper introduces a methodology for simulating single-electron-transistor (SET)-based multiple-valued logics (MVLs). First, a physics-based analytical model for SET is described, and then a procedure for extracting parameters from measured characteristics is explained. After that, simulated and experimental results for basic MVL circuits are compared. As an advanced example of SET-based logics, a latched parallel counter, which is one of the most important components in arithmetic circuits, is newly designed and analyzed by a simulation. It is found that a SET-based 7-3 counter can be constructed with less than 1/10 the number of devices needed for a conventional circuit and can operate at a moderate speed with 1/100 the conventional power consumption.

元の言語 | English |
---|---|

ページ（範囲） | 1818-1826 |

ページ数 | 9 |

ジャーナル | IEICE Transactions on Electronics |

巻 | E87-C |

発行部数 | 11 |

出版物ステータス | Published - 2004 11 |

### ASJC Scopus subject areas

- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering

## フィンガープリント A simulation methodology for single-electron multiple-valued logics and its application to a latched parallel counter' の研究トピックを掘り下げます。これらはともに一意のフィンガープリントを構成します。

## これを引用

*IEICE Transactions on Electronics*,

*E87-C*(11), 1818-1826.