A power-down circuit scheme using data-preserving complementary pass transistor flip-flop for low-power high-performance multi-threshold CMOS LSI

Ki Tae Park, Tomokatsu Mizukusa, Hyo Sig Won, Kyu Myung Choi, Jeong Taek Kong, Hiroyuki Kurino, Mitsumasa Koyanagi

研究成果: Article査読

抄録

A new power-down circuit scheme using data-preserving complementary pass transistor flip-flop circuit for low-power, high-performance Multi-Threshold voltage CMOS (MTCMOS) LSI is presented. The proposed circuit can preserve a stored data during power-down period while maintaining low leakage current without any extra circuit and complex timing design. The flip-flop provides 24% improved delay and 30% less silicon area compared to conventional MTCMOS flip-flop circuit. A 16-bits DSP processor core using the proposed circuit and 0.18 μm CMOS technology was designed. The DSP chip was successfully operated at 120 MHz, 1.65 V and its total leakage current in power-down mode was four orders smaller than conventional DSP chip.

本文言語English
ページ(範囲)645-648
ページ数4
ジャーナルIEICE Transactions on Electronics
E87-C
4
出版ステータスPublished - 2004 4

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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