A power-aware shared cache mechanism based on locality assessment of memory reference for CMPs

Isao Kotera, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi

研究成果: Conference article査読

3 被引用数 (Scopus)

抄録

Chip Multiprocessor (CMP) architectures are the principal trend in current and future microprocessor design, and on-chip shared cache mechanisms play a key role to realize low-power and high performance CMPs. In this paper, we propose a way-allocatable shared cache mechanism, which can achieve both high performance and cache power reduction by using cache partitioning and power gating. We evaluate the performance of our cache mechanism by a cycle accurate simulator, in terms of performance and energy consumption. The performance evaluation results show that the proposed mechanism can properly adjust the control policy from a performance-oriented configuration to a energy-oriented one. The proposed cache mechanism with a performance-oriented parameter setting can reduce energy consumption by 20% while keeping the performance, and the cache with an energy-oriented parameter setting can reduce 54% energy consumption with a performance degradation of 13%.

本文言語English
ページ(範囲)113-120
ページ数8
ジャーナルParallel Architectures and Compilation Techniques - Conference Proceedings, PACT
DOI
出版ステータスPublished - 2007 12 1
イベント8th MEDEA Workshop on MEmory Performance: DEaling with Applications, Systems and Architecture, MEDEA '07, Held in Conjunction with the PACT 2007 Conference - Brasov, Romania
継続期間: 2007 9 162007 9 16

ASJC Scopus subject areas

  • ソフトウェア
  • 理論的コンピュータサイエンス
  • ハードウェアとアーキテクチャ

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