Chip Multiprocessor (CMP) architectures are the principal trend in current and future microprocessor design, and on-chip shared cache mechanisms play a key role to realize low-power and high performance CMPs. In this paper, we propose a way-allocatable shared cache mechanism, which can achieve both high performance and cache power reduction by using cache partitioning and power gating. We evaluate the performance of our cache mechanism by a cycle accurate simulator, in terms of performance and energy consumption. The performance evaluation results show that the proposed mechanism can properly adjust the control policy from a performance-oriented configuration to a energy-oriented one. The proposed cache mechanism with a performance-oriented parameter setting can reduce energy consumption by 20% while keeping the performance, and the cache with an energy-oriented parameter setting can reduce 54% energy consumption with a performance degradation of 13%.
|ジャーナル||Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT|
|出版ステータス||Published - 2007 12 1|
|イベント||8th MEDEA Workshop on MEmory Performance: DEaling with Applications, Systems and Architecture, MEDEA '07, Held in Conjunction with the PACT 2007 Conference - Brasov, Romania|
継続期間: 2007 9 16 → 2007 9 16
ASJC Scopus subject areas