A Novel High-Speed Latching Operation Flip-Flop (HLO-FF) Circuit and its Application to a 19-Gb/s Decision Circuit Using a 0.2-μm GaAs MESFET

Koichi Murata; Taiichi Otsuji; Eiichi Sano; Masanobu Ohhata; Masao Suzuki; Minoru Togashi

doi:10.1109/4.466072

A Novel High-Speed Latching Operation Flip-Flop (HLO-FF) Circuit and its Application to a 19-Gb/s Decision Circuit Using a 0.2-μm GaAs MESFET

Koichi Murata, Taiichi Otsuji, Eiichi Sano, Masanobu Ohhata, Masao Suzuki, Minoru Togashi

研究成果: Article › 査読

34 被引用数 (Scopus)

抄録

This paper describes a novel high-speed flip-flop circuit named the High-speed Latching Operation Flip-Flop (HLO-FF) for GaAs Low-power Source-Coupled FET Logic (LSCFL). We reveal the high-speed operation mechanism of the HLO-FF using newly proposed analytical propagation delay time expressions. A design methodology for series-gated master slave flip-flops and HLO-FF's based on these expressions is also proposed. A SPICE simulation and the fabrication of two decision IC's confirm the accuracy of our analytical method and the high-speed operation of a HLO-FF decision circuit at 19 Gb/s.

本文言語	English
ページ（範囲）	1101-1108
ページ数	8
ジャーナル	IEEE Journal of Solid-State Circuits
巻	30
号	10
DOI	https://doi.org/10.1109/4.466072
出版ステータス	Published - 1995 10月
外部発表	はい

ASJC Scopus subject areas

電子工学および電気工学

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10.1109/4.466072

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引用スタイル

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