A novel design of an FIR filter with a hierachical structure and its LSI implementation

Shogo Nakamura, Akiyoshi Kawahashi, Yoshihiko Horio, Makoto Kotani, Yukio Kadowaki

研究成果: Article査読

抄録

This paper describes a novel design of a linear‐phase FIR filter and its hardware. The proposed filter has a hierarchical building block structure of tapped‐cascaded lower‐order subfilters. Since this architecture can reduce the sensitivity of the rounded filter coefficients, an effective high‐speed processing of the subfilter can be performed by using adders instead of multipliers. Also, identical subfilters are arranged regularly so that the architecture is suitable for LSI implementation. Another important feature is that the design of the higher‐order FIR filter can be replaced with that of the lower‐order subfilter. An LSI implementation of about a 45‐order FIR filter also is described.

本文言語English
ページ(範囲)69-77
ページ数9
ジャーナルElectronics and Communications in Japan (Part III: Fundamental Electronic Science)
74
10
DOI
出版ステータスPublished - 1991
外部発表はい

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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